This invention relates to a thin-film transistor matrix comprising a plurality of thin-film transistors arranged in a matrix array on a common dielectric substrate.
Matrix arrays of thin-film transistors on a common dielectric substrate are used in liquid-crystal displays and other devices. In the following description of a thin-film transistor matrix, the device exemplified is a liquid-crystal display.
A liquid-crystal display operates by using the thin-film transistor in a thin-film transistor matrix to switch individual liquid-crystal pixels directly. An explanation of this operation is given in the Journal of the Television Institute of Japan, Vol. 38 No. 4 (1984), pp. 366-370.
FIG. 1 is a cross-sectional view showing the structure of a liquid-crystal display device as described in the reference cited above.
The liquid-crystal display comprises, on one side, a first dielectric substrate 13 on which a matrix array of thin-film transistors (not shown) are connected to a plurality of display electrodes 11, and on the other side an opposing electrode 15 mounted on a second dielectric substrate 17. The two substrates are separated by a certain gap. A sealing compound 19 holds the two substrates together at their edges, and the gap between them is filled with an injected liquid crystal 21. There are further provided a pair of orienting films 23 and a polarizer 25. The first dielectric substrate 13, supporting the matrix of thin-film transistor in this liquid-crystal display device, is referred to as the thin-film transistor matrix substrate.
FIG. 2 shows an enlarged plan view of part of this first dielectric substrate 13 seen from the direction of the second dielectric substrate 17.
FIG. 3A is a cross-sectional view through the line III--III in FIG. 2.
As shown in FIGS. 2 and/or 3A, arranged on the first dielectric substrate 13 are a matrix of thin-film transistors 39 each comprising a gate electrode 31 that acts as a control electrode, a gate insulation film 41 that provides electrical isolation, an amorphous silicon film 33 that acts as a semiconductor film, and a drain electrode 35 (the first electrode) and a source electrode 37 (the second electrode) which are attached to the surface of the semiconductor film 33. Also shown in FIG. 2 are several display electrodes 11, each of which is connected via the source electrode 37 to its thin-film transistor 39. The gate electrodes 31 of the thin-film transistor 39 in each row (extending horizontally as viewed in FIG. 2) of the matrix array are interconnected, and the drain electrodes 35 in each column (extending vertically as viewed in FIG. 2) are interconnected.
A brief description will now be given of the fabrication process of the above structure on the first dielectric substrate 13. The gate electrodes 31 which act as the control electrodes are formed on a transparent dielectric substrate, such as a glass substrate, interconnected in each row as described above. On this dielectric substrate 13, which includes the gate electrodes 31, are formed first a gate insulation film 41 and then an amorphous silicon film 33. Partial removal of these films leaves a pattern of islands with a layered structure, the layers being the gate insulation film 41 and semiconductor film 33.
Next a metalization process is performed using aluminum, for example, to create the drain electrodes 35 and the source electrodes 37. The drain electrodes 35 in each column are interconnected with each other but are electrically isolated from the source electrodes 37. Finally the display electrodes 11 in the form of a transparent conductive film are formed and a passivation layer (not shown) is applied over the entire dielectric substrate 13, including the display electrodes 11 and thin-film transistors 39, to complete the thin-film transistor matrix.
In the thin-film transistor matrix described above, since the drain electrodes 35 are interconnected in each column and are formed over the layered structure of the island configuration, they must cross a vertical step between the surface of the layered islands of the gate isolation film 41 and the amorphous silicon film 33 and the surface of the insulating substrate 13. More specifically, each of the drain electrodes 35 ascends the step S3 from the dielectric substrate 13 to the surface of the amorphous silicon film 33, then descends the step S4 back to the surface of the dielectric substrate 13.
As an alternative to the configuration shown in FIG. 3A, in which the gate insulation film 41 is confined to the thin-film transistor region, the gate insulation film 41 may be made to extend over the dielectric substrate 13 outside the region of the thin-film transistor 39, as shown in FIG. 3B, which also shows a cross-section through the line III--III in FIG. 2. In this case, each of the drain electrodes 35 ascends the stop S1 from the surface of the gate insulation film 41 to the surface of the amorphous silicon film 33 then descends the step S2 back to the surface of the gate insulation film 41.
Liquid crystal display devices using the thin-film transistor matrix structure of the prior art have suffered from the problem of discontinuities in the drain electrodes at the locations of steps S1, S2, S3, and S4 when step coverage of the drain electrode metal is inadequate.
If the liquid-crystal display device has 640.times.400 pixels, for instance, there are 640.times.400.times.2=512,000 step locations as described above. A discontinuity at any one of these steps makes the liquid-crystal display defective due to one or more nonfunctioning pixels. To avoid the fabrication of defective devices, the probability of a discontinuity at a step must be held to a value well below about 1/500,000. In a thin-film transistor matrix with the structure of the prior art, keeping the probability of a discontinuity at a step (S1, S2, S3, S4 or the like) at such a low level is extremely difficult.